Conference Proceedings

On Error Correction for Nonvolatile PiM, ISCA 2024. Acceptance rate: 19.6%. 

On Gate Flip Errors in Computing-In-Memory, DATE 2024. Acceptance rate: 25%.  

On Endurance of Processing In (Nonvolatile) Memory, ISCA 2023. Acceptance rate: 21.2%. Slides     

PimCity: A Compute in Memory Substrate featuring both Row and Column Parallel Computing, ICRC 2023.  

H-CRAM: In-memory Homomorphic Search Accelerator using Spintronic Computational RAM, SEED 2021. Slides  

Do not Predict - Recompute! How Value Recomputation Can Truly Boost the Performance of Invisible Speculation, SEED 2021.  

CAMeleon: Reconfigurable B(T)CAM in Computational RAM, GLSVLSI 2021. Slides  

CRAFFT: High Resolution FFT Accelerator In Spintronic Computational RAM, DAC 2020. Acceptance rate: 23% Slides  

ACR: Amnesic Checkpointing and Recovery, HPCA 2020. Acceptance rate: 19% Slides  

MOUSE: Inference In Non-volatile Memory for Energy Harvesting Applications, MICRO 2020. Acceptance rate: 19% Talk  Lightning Talk

True In-memory Computing with CRAM: From Technology to Applications, GLSVLSI 2019. 

Barrier Synchronization vs. Voltage Noise: A Quantitative Analysis, IISWC 2019.  

Using Spin-Hall MTJs to Build an Energy-Efficient In-memory Computation Platform, ISQED 2019. 

Special Session: Does Approximation Make Testing Harder (or Easier)?, VTS 2019. 

POWERT Channels: A Novel Class of Covert Communication Exploiting Power Management Vulnerabilities, HPCA 2019. Acceptance rate: 19.7%. Slides 

Mitigation of NBTI Induced Performance Degradation in On-chip Digital LDOs, DATE 2018. Acceptance rate: 23.7%. 

ThermoGater: Thermally-Aware On-Chip Voltage Regulation, ISCA 2017.  Acceptance rate: 16.8%. Slides   

AMNESIAC: Trading Computation for Communication for Energy Efficiency, ASPLOS 2017. Acceptance rate: 17.4%. Slides  Errata

VARIUS-TC: A Modular Architecture-Level Model of Parametric Variation for Thin-Channel Switches, ICCD 2016. Acceptance rate: 28.9%. Slides  Code  Model files

Snatch: Opportunistically Reassigning Power Allocation between Processor and Memory in 3D Stacks, MICRO 2016. Acceptance rate: 22%. 

Comparison of Single-ISA Heterogeneous versus Wide Dynamic Range Processors for Mobile Applications , ICCD 2015. Acceptance rate: 31%. Slides

Accordion: Toward Soft Near-threshold Voltage Computing, HPCA 2014. Acceptance rate: 25.6%. Slides 

EnergySmart: Toward Energy-Efficient Many-Cores for Near-Threshold Computing, HPCA 2013. Acceptance rate: 21%. Slides

VARIUS-NTV: A Microarchitectural Model to Capture the Increased Sensitivity of Many-Cores to Process Variations at Near-Threshold Voltages, DSN 2012. Acceptance rate: 17%. Slides  Code  Techreport

LeadOut: Composing Low Overhead Frequency Enhancing Techniques for Single Thread Performance in Configurable Multicores, HPCA 2010. Acceptance rate: 19%. Slides 

The BubbleWrap Many-Core: Popping Cores for Sequential Acceleration, MICRO 2009. Acceptance rate: 24.9%. Best Paper Award. Slides 

Accurate Microarchitecture-level Fault Modeling for Studying Hardware Faults, HPCA 2009. Acceptance rate: 19%. 

Blueshift: Designing Processors for Timing Speculation from the Ground up, HPCA 2009. Acceptance rate: 19%. 


A Stochastic Computing Scheme of Embedding Random Bit Generation and Processing in Computational Random Access Memory (SC-CRAM), IEEE JXCDC 2023.  

On Variable Strength Quantum ECC, IEEE CAL 2022.

Benchmarking Quantum Computers and the Impact of Quantum Noise, ACM Computing Surveys 2022.  QuantumOps

GeNVoM: Read Mapping Near Nonvolatile Memory, IEEE ACM Transactions on Computational Biology and Bioinformatics 2022.  

Energy Efficient and Reliable Inference in Nonvolatile Memory under Extreme Operating Conditions , ACM TECS 2022.  

CRAM-Seq: Accelerating RNA-Seq Abundance Quantification Using Computational RAM, IEEE TETC 2022.  

A Day In the Life of a Quantum Error, IEEE CAL 2021. 

Cryogenic PIM: Challenges and Opportunities, IEEE CAL 2021.  

Spiking Networks in Spintronic Computational RAM, ACM TACO 2021. 

Exploring the 3D X-Point as an In-Memory Computing Accelerator, IEEE JXCDC 2021. 

A DNA Read Alignment Accelerator Based on Computational RAM, IEEE JXCDC 2020. 

Analyzing the Effects of Interconnect Parasitics in the STT CRAM In-Memory Computational Platform, IEEE JXCDC 2020. 

Voltage Noise Mitigation with Barrier Approximation, IEEE CAL 2020.  

Dual-precision Fixed-Point Arithmetic for Low-power Ray-triangle Intersections, Computers & Graphics 2020.  

PIMBALL: Binary Neural Networks in Spintronic Memory, ACM TACO 2020. 

Spintronic In-Memory Pattern Matching, IEEE JXCDC 2019. Appendix

Trading Computation for Communication: A Taxonomy of Data Recomputation Techniques, IEEE TETC 2018.  

Exploiting Algorithmic NoiseTolerance for Scalable On-Chip Voltage Regulation, IEEE TVLSI 2018. 

A New Class of Covert Channels Exploiting Power Management Vulnerabilities, IEEE CAL 2018. 

Toward Dynamic Precision Scaling, IEEE Micro Magazine Special Issue on Approximate Computing, 2018. 

In-Memory Processing on the Spintronic CRAM: From Hardware Design to Application Mapping, IEEE TC Special Issue on Emerging Non-volatile Memory Technologies: from Devices to Architectures and Systems, 2018. 

On Memory System Design for Stochastic Computing, IEEE CAL 2018. 

Approximate Communication: Approximation Techniques for Communication Reduction in Parallel Systems, ACM Computing Surveys 2018. 

On Approximate Speculative Lock Elision, IEEE TMSCS 2018. 

Efficient In-Memory Processing Using Spintronics, IEEE CAL 2017. 

Efficiency, Stability, and Reliability Implications of Unbalanced Current Sharing among Distributed On-Chip Voltage Regulators, IEEE TVLSI 2017. 

Accuracy Bugs: A New Class of Concurrency Bugs to Exploit Algorithmic Noise Tolerance, ACM TACO 2016.  HiPEAC Presentation   

System-Level Power Analysis of a Multicore Multipower Domain Processor with on-chip Voltage Regulators, IEEE TVLSI 2016. 

Decoupling Control and Data Processing for Approximate Near-threshold Voltage Computing, IEEE Micro Magazine Special Issue on Heterogeneous Computing, 2015. 

Low-Cost Per-Core Voltage Domain Support for Power-Constrained High-Performance Processors, IEEE TVLSI, 2014. 

Coping With Parametric Variation at Near-Threshold Voltages, IEEE Micro Magazine Special Issue on Reliability, 2013. 

Book Chapters

Approximate Ultra-low Voltage Many-Core Processor Design, Approximate Circuits, 2019. 


Quantum Computing: An Overview Across the System Stack, 2019. 

Workshops & Posters

AISC: Approximate Instruction Set Computer, ASPLOS WAX 2018. Slides  arXiv

BioArch: A Reconfigurable Hardware Accelerator Designed for Bioinformatics Workloads, talk in The Cold Spring Harbor Laboratory Conference on Genome Informatics, November 2017. 

De novo Transcriptome Sequencing via Binary Neural Networks, poster in The Southern California Machine Learning Symposium (SoCal ML), October 2017. 

On Quantification of Accuracy Loss in Approximate Computing, ISCA WDDD 2015. Slides   Accurax Code

AMNESIAC: Amnesic Automatic Computer, ASPLOS Wild and Crazy Ideas 2014. Slides

BubbleWrap: Popping CMP Cores for Per-Thread Performance, ASPLOS Wild and Crazy Ideas 2009. Best Idea Award. 

Automatic Verilog Code Generation Through Grammatical Evolution, GECCO Undergraduate Student Workshop 2005.